1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a technique of designing a reset signal in the semiconductor integrated circuit.
2. Description of the Related Art
In designing a large-scale LSI, as a method to effectively utilize intellectual property and reduce a design period, known is hierarchical design (hierarchical layout design) in which physical design (layout design) of each lower hierarchy block is independently implemented, and physical design of the entire LSI (upper hierarchy) is implemented, using the lower hierarchy blocks (including hard macro which is a library of layout data) whose physical design has been completed.
When the physical design of the lower hierarchy blocks is completed, the signal input time of an input signal (setup time and hold time) is prescribed for a signal input pin of each of the lower hierarchy blocks in order to guarantee normal operations of the lower hierarchy blocks, in consideration of manufacturing process conditions, an operational temperature range, an operational voltage range, and so on as well as the clock delay time from a clock input pin up to each flip-flop and the signal delay time from each signal input pin to each flip-flop. In upper hierarchy design, physical design of portions except the lower hierarchy blocks in the LSI (wiring among the lower hierarchy blocks and so on) is implemented so as to satisfy the setup times and the hold times that are prescribed respectively for the signal input pins of the lower hierarchy blocks.
Further, Japanese Unexamined Patent Application Publication No. Hei 8-76893 discloses a technology of surely resetting a synchronous reset circuit in response to a reset pulse and a clock irrespective of the duration of the reset pulse or the delay of the clock.
Japanese Unexamined Patent Application Publication No. Hei 7-168652 discloses a synchronous reset circuit realizing reduction in circuit scale and reduction in the number of pins of a data processor. In this synchronous reset circuit, an asynchronous reset signal is synchronized with a clock by a synchronization circuit, and from the reset signal synchronous with the clock, a plurality of delay circuits generate a plurality of reset signals different in activation timing, which are then supplied to a plurality of flip-flop groups respectively. This causes the plural flip-flop groups to be reset at different timings from one another. Further, a reset ending circuit synchronizes deactivation timings of the plural reset signals, so that all the flip-flops are concurrently released from the reset state.
Japanese Unexamined Patent Application Publication No. Hei 11-88306 discloses a technology of generating a synchronizing pulse signal from an asynchronous pulse signal even when a clock signal with a longer cycle than the pulse width of the asynchronous pulse signal is used.
The setup time and the hold time of an input signal that are prescribed for a signal input pin of a lower hierarchy block are proper values determined according to an internal structure of the lower hierarchy block. Therefore, if hierarchical design is implemented by combining a large number of lower hierarchy blocks, timing constraint (clock cycle or the like) cannot be sometimes satisfied (state of difficulty in timing closure) in upper hierarchy design since the setup time and the hold time are prescribed at different values respectively for the signal input pins of the plural lower hierarchy blocks receiving a common signal.
For example, a reset signal is a high fan-out signal (high fan-out net) propagated from an upper hierarchy to flip-flops in each of the lower hierarchy blocks via a reset input pin of each of the lower hierarchy blocks. Further, the number of the flip-flops included in the lower hierarchy block and circuit scale or the clock delay time in the lower hierarchy block greatly differ among lower hierarchy blocks. Therefore, there tends to occur variation in the setup time and the hold time of the reset signal that are prescribed for the reset input pins of the respective lower hierarchy blocks. Further, in order to surely prevent a malfunction of an LSI, it is generally necessary to implement the design of the reset signal so that all the flip-flops can be released from the reset state during the same clock cycle. Therefore, the smaller the clock cycle is, the more severe timing constraint on the reset signal is.
One of known methods of adjusting the timing of the high fan-out signal such as the reset signal is a method of adopting a tree structure to paths of the reset signal, as is often applied to a clock signal. This method is effective in a case where the reset signals are collectively designed in the entire LSI, but in a case of the hierarchical design, the tree structure cannot be adopted to portions included in the lower hierarchy blocks since the paths of the reset signal include inner parts of the lower hierarchy blocks whose physical design has been completed. For this reason, a timing adjustment effect by the adoption of the tree structure is limited. Consequently, it requires a large number of man-hours to design the reset signal. This results in a longer design period of the LSI and increased product cost.
Another known method is a method of suppressing the setup time and the hold time of an input signal that are prescribed for a signal input pin. For example, by reducing the number of logic stages between the signal input pin and a first-stage flip-flop as much as possible, variation in the setup time and the hold time of the input signal can be reduced. This method is effective for a general signal synchronizing with a clock signal, but is not effective for a signal such as a reset signal that is not synchronized with the clock signal and is supplied from a reset input pin directly to a reset pin of each flip-flop.